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Searched refs:mmRLC_LB_THR_CONFIG_4 (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c	`1721 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 \| 0x40 << 8 \| 0x02FA << 16)); 1770 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 \| 0x27 << 8 \| 0x02FA << 16));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`6230 #define mmRLC_LB_THR_CONFIG_4 0x4cba`
gc_9_1_offset.h	`6452 #define mmRLC_LB_THR_CONFIG_4 0x4cba`
gc_9_2_1_offset.h	`6428 #define mmRLC_LB_THR_CONFIG_4 0x4cba`

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