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    Searched refs:mmRLC_SPARE_INT_BASE_IDX (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h 83 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6263 #define mmRLC_SPARE_INT_BASE_IDX 1
gc_9_1_offset.h 6485 #define mmRLC_SPARE_INT_BASE_IDX 1
gc_9_2_1_offset.h 6461 #define mmRLC_SPARE_INT_BASE_IDX 1
gc_10_1_0_offset.h 9573 #define mmRLC_SPARE_INT_BASE_IDX 1
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