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    Searched refs:mmRLC_SRM_CNTL (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 1856 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1859 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
amdgpu_gfx_v9_0.c 2652 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2654 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h 1454 #define mmRLC_SRM_CNTL 0xec80
gfx_8_1_d.h 1450 #define mmRLC_SRM_CNTL 0xec80
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 52 { 0x00000002, mmRLC_SRM_CNTL },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6138 #define mmRLC_SRM_CNTL 0x4c80
gc_9_1_offset.h 6360 #define mmRLC_SRM_CNTL 0x4c80
gc_9_2_1_offset.h 6336 #define mmRLC_SRM_CNTL 0x4c80
gc_10_1_0_offset.h 9454 #define mmRLC_SRM_CNTL 0x4c80
    [all...]

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