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    Searched refs:mmSCRATCH_REG0_BASE_IDX (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h 214 #define mmSCRATCH_REG0_BASE_IDX 1
gc_9_0_offset.h 4639 #define mmSCRATCH_REG0_BASE_IDX 1
gc_9_1_offset.h 4869 #define mmSCRATCH_REG0_BASE_IDX 1
gc_9_2_1_offset.h 4825 #define mmSCRATCH_REG0_BASE_IDX 1
gc_10_1_0_offset.h 7105 #define mmSCRATCH_REG0_BASE_IDX 1
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h 81 uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \

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