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Searched refs:mmSCRATCH_REG1_BASE_IDX (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h	`82 uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \ 104 uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ 105 uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h	`216 #define mmSCRATCH_REG1_BASE_IDX 1`
gc_9_0_offset.h	`4641 #define mmSCRATCH_REG1_BASE_IDX 1`
gc_9_1_offset.h	`4871 #define mmSCRATCH_REG1_BASE_IDX 1`
gc_9_2_1_offset.h	`4827 #define mmSCRATCH_REG1_BASE_IDX 1`
gc_10_1_0_offset.h	`7107 #define mmSCRATCH_REG1_BASE_IDX 1 [all...]`

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