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Searched refs:mmSCRATCH_REG3 (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h	`219 #define mmSCRATCH_REG3 0x2043`
gc_9_0_offset.h	`4644 #define mmSCRATCH_REG3 0x2043`
gc_9_1_offset.h	`4874 #define mmSCRATCH_REG3 0x2043`
gc_9_2_1_offset.h	`4830 #define mmSCRATCH_REG3 0x2043`
gc_10_1_0_offset.h	`7110 #define mmSCRATCH_REG3 0x2043 [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h	`105 uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h	`1186 #define mmSCRATCH_REG3 0x2143`
gfx_7_0_d.h	`409 #define mmSCRATCH_REG3 0xc043`
gfx_7_2_d.h	`421 #define mmSCRATCH_REG3 0xc043`
gfx_8_0_d.h	`459 #define mmSCRATCH_REG3 0xc043`
gfx_8_1_d.h	`459 #define mmSCRATCH_REG3 0xc043`

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