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Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h	`264 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2`
sdma0_4_0_offset.h	`268 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2`
sdma0_4_2_2_offset.h	`268 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2`
sdma0_4_2_offset.h	`264 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h	`195 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486`
oss_2_0_d.h	`254 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486`
oss_3_0_1_d.h	`222 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486`
oss_3_0_d.h	`347 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v3_0.c	`726 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],`
amdgpu_sdma_v5_0.c	`656 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),`
amdgpu_sdma_v4_0.c	`1148 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h	`258 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 [all...]`

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