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Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h	`266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3`
sdma0_4_0_offset.h	`270 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3`
sdma0_4_2_2_offset.h	`270 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3`
sdma0_4_2_offset.h	`266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h	`196 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487`
oss_2_0_d.h	`255 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487`
oss_3_0_1_d.h	`223 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487`
oss_3_0_d.h	`348 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v3_0.c	`724 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],`
amdgpu_sdma_v5_0.c	`654 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),`
amdgpu_sdma_v4_0.c	`1146 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h	`260 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 [all...]`

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