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    Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_CNTL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 220 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
sdma0_4_0_offset.h 224 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
sdma0_4_2_2_offset.h 224 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
sdma0_4_2_offset.h 220 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v4_0.c 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
260 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
1150 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1154 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
amdgpu_sdma_v5_0.c 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
659 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
663 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
amdgpu_sdma_v3_0.c 728 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
740 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 194 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
oss_2_0_d.h 253 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
oss_3_0_1_d.h 221 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
oss_3_0_d.h 346 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 215 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
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