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    Searched refs:mmSDMA0_PAGE_RB_WPTR_POLL_CNTL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_0_offset.h 310 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7
sdma0_4_2_2_offset.h 310 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df
sdma0_4_2_offset.h 306 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v4_0.c 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
1241 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1245 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
amdgpu_sdma_v5_0.c 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 300 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7
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