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Searched refs:mmSDMA0_RLC0_MINOR_PTR_UPDATE (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_arcturus.c	`172 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 184 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 221 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)`
amdgpu_amdkfd_gfx_v10.c	`470 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 482 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 519 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)`
amdgpu_amdkfd_gfx_v9.c	`458 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 470 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 507 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h	`354 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175`
sdma0_4_0_offset.h	`442 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175`
sdma0_4_2_2_offset.h	`442 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165`
sdma0_4_2_offset.h	`438 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h	`430 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 [all...]`

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