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    Searched refs:mmSDMA0_RLC0_RB_BASE (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_arcturus.c 186 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
amdgpu_amdkfd_gfx_v10.c 484 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
amdgpu_amdkfd_gfx_v7.c 365 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
amdgpu_amdkfd_gfx_v8.c 351 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
amdgpu_amdkfd_gfx_v9.c 472 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 294 #define mmSDMA0_RLC0_RB_BASE 0x0141
sdma0_4_0_offset.h 382 #define mmSDMA0_RLC0_RB_BASE 0x0141
sdma0_4_2_2_offset.h 382 #define mmSDMA0_RLC0_RB_BASE 0x0131
sdma0_4_2_offset.h 378 #define mmSDMA0_RLC0_RB_BASE 0x0141
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 217 #define mmSDMA0_RLC0_RB_BASE 0x3501
oss_2_0_d.h 271 #define mmSDMA0_RLC0_RB_BASE 0x3501
oss_3_0_1_d.h 256 #define mmSDMA0_RLC0_RB_BASE 0x3501
oss_3_0_d.h 378 #define mmSDMA0_RLC0_RB_BASE 0x3501
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 371 #define mmSDMA0_RLC0_RB_BASE 0x0141
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