HomeSort by: relevance | last modified time | path
    Searched refs:mmSDMA0_RLC0_RB_CNTL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_arcturus.c 90 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
123 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
146 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
196 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
216 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
244 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
265 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
267 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
281 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
    [all...]
amdgpu_amdkfd_gfx_v10.c 219 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
222 * base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL
227 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
231 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
444 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
494 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
514 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
564 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
693 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
    [all...]
amdgpu_amdkfd_gfx_v9.c 229 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
234 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
432 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
482 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
502 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
552 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
623 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
625 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
639 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
    [all...]
amdgpu_amdkfd_gfx_v7.c 336 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
375 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
395 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
439 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
561 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
563 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
577 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
578 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
amdgpu_amdkfd_gfx_v8.c 322 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
361 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
381 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
434 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
559 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
561 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
575 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
576 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
cikd.h 567 #define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL)
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 292 #define mmSDMA0_RLC0_RB_CNTL 0x0140
sdma0_4_0_offset.h 380 #define mmSDMA0_RLC0_RB_CNTL 0x0140
sdma0_4_2_2_offset.h 380 #define mmSDMA0_RLC0_RB_CNTL 0x0130
sdma0_4_2_offset.h 376 #define mmSDMA0_RLC0_RB_CNTL 0x0140
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 216 #define mmSDMA0_RLC0_RB_CNTL 0x3500
oss_2_0_d.h 270 #define mmSDMA0_RLC0_RB_CNTL 0x3500
oss_3_0_1_d.h 255 #define mmSDMA0_RLC0_RB_CNTL 0x3500
oss_3_0_d.h 377 #define mmSDMA0_RLC0_RB_CNTL 0x3500
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 369 #define mmSDMA0_RLC0_RB_CNTL 0x0140
    [all...]

Completed in 57 milliseconds