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    Searched refs:mmSDMA0_RLC0_RB_RPTR (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_arcturus.c 167 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
285 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
amdgpu_amdkfd_gfx_v10.c 465 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
713 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
amdgpu_amdkfd_gfx_v7.c 354 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
581 m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
amdgpu_amdkfd_gfx_v8.c 340 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
579 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
amdgpu_amdkfd_gfx_v9.c 453 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
643 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 298 #define mmSDMA0_RLC0_RB_RPTR 0x0143
sdma0_4_0_offset.h 386 #define mmSDMA0_RLC0_RB_RPTR 0x0143
sdma0_4_2_2_offset.h 386 #define mmSDMA0_RLC0_RB_RPTR 0x0133
sdma0_4_2_offset.h 382 #define mmSDMA0_RLC0_RB_RPTR 0x0143
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 219 #define mmSDMA0_RLC0_RB_RPTR 0x3503
oss_2_0_d.h 273 #define mmSDMA0_RLC0_RB_RPTR 0x3503
oss_3_0_1_d.h 258 #define mmSDMA0_RLC0_RB_RPTR 0x3503
oss_3_0_d.h 380 #define mmSDMA0_RLC0_RB_RPTR 0x3503
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 375 #define mmSDMA0_RLC0_RB_RPTR 0x0143
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