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    Searched refs:mmSDMA0_RLC0_RB_WPTR (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_arcturus.c 174 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
179 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
amdgpu_amdkfd_gfx_v10.c 472 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
477 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
amdgpu_amdkfd_gfx_v7.c 358 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
360 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
amdgpu_amdkfd_gfx_v8.c 344 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
346 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
amdgpu_amdkfd_gfx_v9.c 460 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
465 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 302 #define mmSDMA0_RLC0_RB_WPTR 0x0145
sdma0_4_0_offset.h 390 #define mmSDMA0_RLC0_RB_WPTR 0x0145
sdma0_4_2_2_offset.h 390 #define mmSDMA0_RLC0_RB_WPTR 0x0135
sdma0_4_2_offset.h 386 #define mmSDMA0_RLC0_RB_WPTR 0x0145
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 220 #define mmSDMA0_RLC0_RB_WPTR 0x3504
oss_2_0_d.h 274 #define mmSDMA0_RLC0_RB_WPTR 0x3504
oss_3_0_1_d.h 259 #define mmSDMA0_RLC0_RB_WPTR 0x3504
oss_3_0_d.h 381 #define mmSDMA0_RLC0_RB_WPTR 0x3504
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 379 #define mmSDMA0_RLC0_RB_WPTR 0x0145
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