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Searched refs:mmSDMA0_RLC0_RB_WPTR_HI (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_arcturus.c	`176 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 181 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,`
amdgpu_amdkfd_gfx_v10.c	`474 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 479 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,`
amdgpu_amdkfd_gfx_v9.c	`462 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 467 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h	`304 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146`
sdma0_4_0_offset.h	`392 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146`
sdma0_4_2_2_offset.h	`392 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0136`
sdma0_4_2_offset.h	`388 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h	`381 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 [all...]`

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