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    Searched refs:mmSDMA0_RLC0_RB_WPTR_POLL_CNTL (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_1_offset.h 306 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
sdma0_4_0_offset.h 394 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
sdma0_4_2_2_offset.h 394 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137
sdma0_4_2_offset.h 390 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 221 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
oss_2_0_d.h 275 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
oss_3_0_1_d.h 260 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
oss_3_0_d.h 382 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v4_0.c 103 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
262 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
amdgpu_sdma_v5_0.c 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 383 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
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