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    Searched refs:mmSDMA0_RLC5_RB_WPTR_POLL_CNTL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_2_2_offset.h 814 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef
sdma0_4_2_offset.h 810 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v5_0.c 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
amdgpu_sdma_v4_0.c 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 798 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327
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