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Searched refs:mmSDMA1_GFX_RB_WPTR_POLL_CNTL (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h	`303 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685`
oss_2_0_d.h	`344 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685`
oss_3_0_1_d.h	`392 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685`
oss_3_0_d.h	`496 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma1/
sdma1_4_0_offset.h	`216 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087`
sdma1_4_2_2_offset.h	`216 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087`
sdma1_4_2_offset.h	`212 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v4_0.c	`110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),`
amdgpu_sdma_v5_0.c	`85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h	`1214 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687 [all...]`

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