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    Searched refs:mmSDMA1_RLC1_IB_CNTL (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_vi.c 117 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
257 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
amdgpu_sdma_v3_0.c 97 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
115 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
135 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
149 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
165 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
amdgpu_sdma_v4_0.c 116 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_d.h 363 #define mmSDMA1_RLC1_IB_CNTL 0x378a
oss_2_0_d.h 394 #define mmSDMA1_RLC1_IB_CNTL 0x378a
oss_3_0_1_d.h 474 #define mmSDMA1_RLC1_IB_CNTL 0x378a
oss_3_0_d.h 572 #define mmSDMA1_RLC1_IB_CNTL 0x378a
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma1/
sdma1_4_0_offset.h 476 #define mmSDMA1_RLC1_IB_CNTL 0x01aa
sdma1_4_2_2_offset.h 476 #define mmSDMA1_RLC1_IB_CNTL 0x0192
sdma1_4_2_offset.h 472 #define mmSDMA1_RLC1_IB_CNTL 0x01aa
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 1471 #define mmSDMA1_RLC1_IB_CNTL 0x07aa
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