HomeSort by: relevance | last modified time | path
    Searched refs:mmSH_MEM_BASES (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 140 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
amdgpu_amdkfd_gfx_v7.c 169 WREG32(mmSH_MEM_BASES, sh_mem_bases);
amdgpu_amdkfd_gfx_v8.c 126 WREG32(mmSH_MEM_BASES, sh_mem_bases);
amdgpu_amdkfd_gfx_v9.c 136 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
amdgpu_gfx_v8_0.c 3712 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3793 WREG32(mmSH_MEM_BASES, 0);
3801 WREG32(mmSH_MEM_BASES, tmp);
amdgpu_gfx_v9_0.c 2425 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
2499 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
2510 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
amdgpu_gfx_v10_0.c 1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1759 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
amdgpu_gfx_v7_0.c 1886 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1991 WREG32(mmSH_MEM_BASES, sh_mem_base);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 1944 #define mmSH_MEM_BASES 0x230a
gfx_7_2_d.h 1965 #define mmSH_MEM_BASES 0x230a
gfx_8_0_d.h 2164 #define mmSH_MEM_BASES 0x230a
gfx_8_1_d.h 2132 #define mmSH_MEM_BASES 0x230a
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 408 #define mmSH_MEM_BASES 0x030a
gc_9_1_offset.h 402 #define mmSH_MEM_BASES 0x030a
gc_9_2_1_offset.h 398 #define mmSH_MEM_BASES 0x030a
gc_10_1_0_offset.h 2444 #define mmSH_MEM_BASES 0x10aa
    [all...]

Completed in 339 milliseconds