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Searched refs:mmSMU_BIF_VDDGFX_PWR_STATUS (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_5_0_d.h	`106 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8`
bif_5_1_d.h	`97 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbif/
nbif_6_1_offset.h	`859 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0e33 // duplicate`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
nbio_6_1_offset.h	`2496 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113`
nbio_7_0_offset.h	`4378 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113`

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