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    Searched refs:mmSMU_MP1_SRBM2P_RESP_0 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_d.h 268 #define mmSMU_MP1_SRBM2P_RESP_0 0x1d0
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu8_smumgr.c 97 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);

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