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    Searched refs:mmSPI_CONFIG_CNTL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si.c 82 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
138 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
321 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
359 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
408 mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000,
amdgpu_gfx_v7_0.c 2003 tmp = RREG32(mmSPI_CONFIG_CNTL);
2005 WREG32(mmSPI_CONFIG_CNTL, tmp);
amdgpu_gfx_v10_0.c 3720 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3723 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1196 #define mmSPI_CONFIG_CNTL 0x2440
gfx_7_0_d.h 1454 #define mmSPI_CONFIG_CNTL 0x2440
gfx_7_2_d.h 1475 #define mmSPI_CONFIG_CNTL 0x2440
gfx_8_0_d.h 1665 #define mmSPI_CONFIG_CNTL 0x2440
gfx_8_1_d.h 1633 #define mmSPI_CONFIG_CNTL 0x2440
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 5134 #define mmSPI_CONFIG_CNTL 0x2440
gc_9_1_offset.h 5364 #define mmSPI_CONFIG_CNTL 0x2440
gc_9_2_1_offset.h 5322 #define mmSPI_CONFIG_CNTL 0x2440
gc_10_1_0_offset.h 2588 #define mmSPI_CONFIG_CNTL 0x11e0
    [all...]

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