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Searched refs:mmSPI_GDBG_WAVE_CNTL2_BASE_IDX (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2719 #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0`
gc_9_2_1_offset.h	`2905 #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0`

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