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    Searched refs:mmSPI_GDBG_WAVE_CNTL3 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	2720 #define mmSPI_GDBG_WAVE_CNTL3 0x11d5
gc_9_2_1_offset.h	2906 #define mmSPI_GDBG_WAVE_CNTL3 0x11d5

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