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Searched refs:mmSPI_PS_INPUT_CNTL_0 (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h	`1222 #define mmSPI_PS_INPUT_CNTL_0 0xA191`
gfx_7_0_d.h	`1363 #define mmSPI_PS_INPUT_CNTL_0 0xa191`
gfx_7_2_d.h	`1380 #define mmSPI_PS_INPUT_CNTL_0 0xa191`
gfx_8_0_d.h	`1559 #define mmSPI_PS_INPUT_CNTL_0 0xa191`
gfx_8_1_d.h	`1527 #define mmSPI_PS_INPUT_CNTL_0 0xa191`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`3858 #define mmSPI_PS_INPUT_CNTL_0 0x0191`
gc_9_1_offset.h	`4088 #define mmSPI_PS_INPUT_CNTL_0 0x0191`
gc_9_2_1_offset.h	`4040 #define mmSPI_PS_INPUT_CNTL_0 0x0191`
gc_10_1_0_offset.h	`6242 #define mmSPI_PS_INPUT_CNTL_0 0x0191 [all...]`

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