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Searched refs:mmSPI_PS_INPUT_CNTL_20 (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h	`1234 #define mmSPI_PS_INPUT_CNTL_20 0xA1A5`
gfx_7_0_d.h	`1383 #define mmSPI_PS_INPUT_CNTL_20 0xa1a5`
gfx_7_2_d.h	`1400 #define mmSPI_PS_INPUT_CNTL_20 0xa1a5`
gfx_8_0_d.h	`1579 #define mmSPI_PS_INPUT_CNTL_20 0xa1a5`
gfx_8_1_d.h	`1547 #define mmSPI_PS_INPUT_CNTL_20 0xa1a5`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`3898 #define mmSPI_PS_INPUT_CNTL_20 0x01a5`
gc_9_1_offset.h	`4128 #define mmSPI_PS_INPUT_CNTL_20 0x01a5`
gc_9_2_1_offset.h	`4080 #define mmSPI_PS_INPUT_CNTL_20 0x01a5`
gc_10_1_0_offset.h	`6282 #define mmSPI_PS_INPUT_CNTL_20 0x01a5 [all...]`

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