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    Searched refs:mmSQC_DCACHE_UTCL1_CNTL1 (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	654 #define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5
gc_9_1_offset.h	648 #define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5
gc_9_2_1_offset.h	626 #define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5

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