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Searched refs:mmSQC_EDC_PARITY_CNT3 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_4.c	`73 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 0, 4, 6 }, 263 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 269 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 280 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 284 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 295 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 301 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 312 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 316 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h	`160 #define mmSQC_EDC_PARITY_CNT3 0x032e`

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