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Searched refs:mmSQ_CMD (Results 1 - 15 of 15) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c	`757 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);`
amdgpu_amdkfd_gfx_v7.c	`647 WREG32(mmSQ_CMD, sq_cmd);`
amdgpu_amdkfd_gfx_v8.c	`620 WREG32(mmSQ_CMD, sq_cmd);`
amdgpu_amdkfd_gfx_v9.c	`687 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);`
amdgpu_gfx_v7_0.c	`4146 WREG32(mmSQ_CMD, value);`
amdgpu_gfx_v8_0.c	`6507 WREG32(mmSQ_CMD, value);`
amdgpu_gfx_v9_0.c	`5376 WREG32_SOC15(GC, 0, mmSQ_CMD, value);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`1903 #define mmSQ_CMD 0x237b`
gfx_7_2_d.h	`1924 #define mmSQ_CMD 0x237b`
gfx_8_0_d.h	`2122 #define mmSQ_CMD 0x237b`
gfx_8_1_d.h	`2090 #define mmSQ_CMD 0x237b`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`460 #define mmSQ_CMD 0x037b`
gc_9_1_offset.h	`454 #define mmSQ_CMD 0x037b`
gc_9_2_1_offset.h	`444 #define mmSQ_CMD 0x037b`
gc_10_1_0_offset.h	`2532 #define mmSQ_CMD 0x111b [all...]`

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