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    Searched refs:mmSQ_EDC_INFO (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h 168 #define mmSQ_EDC_INFO 0x03a5
gc_9_0_offset.h 564 #define mmSQ_EDC_INFO 0x03a5
gc_9_1_offset.h 558 #define mmSQ_EDC_INFO 0x03a5
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_4.c 67 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16 },
amdgpu_gfx_v8_0.c 1514 mmSQ_EDC_INFO,
6827 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
amdgpu_gfx_v9_0.c 4132 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16},
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h 2101 #define mmSQ_EDC_INFO 0x23a3
gfx_8_1_d.h 2069 #define mmSQ_EDC_INFO 0x23a3

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