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    Searched refs:mmTCC_DSM_CNTL2_BASE_IDX (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	1766 #define mmTCC_DSM_CNTL2_BASE_IDX 0
gc_9_1_offset.h	2051 #define mmTCC_DSM_CNTL2_BASE_IDX 0
gc_9_2_1_offset.h	1987 #define mmTCC_DSM_CNTL2_BASE_IDX 0

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