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Searched refs:mmUVD_CTX_INDEX (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`42 #define mmUVD_CTX_INDEX 0x3D28`
uvd_4_2_d.h	`42 #define mmUVD_CTX_INDEX 0x3d28`
uvd_5_0_d.h	`48 #define mmUVD_CTX_INDEX 0x3d28`
uvd_6_0_d.h	`64 #define mmUVD_CTX_INDEX 0x3d28`
uvd_7_0_offset.h	`142 #define mmUVD_CTX_INDEX 0x0528`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`302 #define mmUVD_CTX_INDEX 0x0528`
vcn_2_0_0_offset.h	`502 #define mmUVD_CTX_INDEX 0x01e8`
vcn_2_5_offset.h	`605 #define mmUVD_CTX_INDEX 0x00c7`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_soc15.c	`180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);`
amdgpu_vi.c	`171 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 182 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));`
amdgpu_cik.c	`136 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 147 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));`

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