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Searched refs:mmUVD_DPG_LMA_CTL (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn.h	`72 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 84 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 116 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \ 127 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`38 #define mmUVD_DPG_LMA_CTL 0x00d1`
vcn_2_0_0_offset.h	`396 #define mmUVD_DPG_LMA_CTL 0x0011`
vcn_2_5_offset.h	`411 #define mmUVD_DPG_LMA_CTL 0x0011`

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