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    Searched refs:mmUVD_DPG_LMA_MASK (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn.h 71 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 42 #define mmUVD_DPG_LMA_MASK 0x00d3
vcn_2_0_0_offset.h 400 #define mmUVD_DPG_LMA_MASK 0x0013
vcn_2_5_offset.h 415 #define mmUVD_DPG_LMA_MASK 0x0013

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