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Searched refs:mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_2_0_0_offset.h	`149 #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0`
vcn_2_5_offset.h	`164 #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0`

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