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Searched refs:mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_7_0_offset.h	`179 #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`367 #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1`
vcn_2_0_0_offset.h	`617 #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1`
vcn_2_5_offset.h	`688 #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1`

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