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Searched refs:mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_4_0_offset.h	`164 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v4_0.c	`261 mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), tmr_mc_addr >> 8); 268 mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), 630 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), 636 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),`
amdgpu_vce_v3_0.c	`53 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616 546 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));`

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