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    Searched refs:mmVCE_MMSCH_VF_MAILBOX_HOST (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_4_0_offset.h 198 #define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v4_0.c 191 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
amdgpu_uvd_v7_0.c 751 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);

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