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Searched refs:mmVCE_RB_BASE_HI (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h	`40 #define mmVCE_RB_BASE_HI 0x8061`
vce_2_0_d.h	`44 #define mmVCE_RB_BASE_HI 0x8061`
vce_3_0_d.h	`44 #define mmVCE_RB_BASE_HI 0x8061`
vce_4_0_offset.h	`84 #define mmVCE_RB_BASE_HI 0x0a61`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v2_0.c	`252 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));`
amdgpu_vce_v4_0.c	`242 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), 352 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));`
amdgpu_vce_v3_0.c	`289 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));`

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