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    Searched refs:mmVCE_RB_BASE_HI2 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h 41 #define mmVCE_RB_BASE_HI2 0x805C
vce_2_0_d.h 39 #define mmVCE_RB_BASE_HI2 0x805c
vce_3_0_d.h 39 #define mmVCE_RB_BASE_HI2 0x805c
vce_4_0_offset.h 74 #define mmVCE_RB_BASE_HI2 0x0a5c
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v2_0.c 259 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
amdgpu_vce_v3_0.c 296 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
amdgpu_vce_v4_0.c 360 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));

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