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    Searched refs:mmVCE_RB_BASE_HI3 (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_3_0_d.h 52 #define mmVCE_RB_BASE_HI3 0x80d5
vce_4_0_offset.h 100 #define mmVCE_RB_BASE_HI3 0x0ad5
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v3_0.c 303 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
amdgpu_vce_v4_0.c 368 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));

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