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    Searched refs:mmVCE_RB_RPTR3 (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_3_0_d.h 54 #define mmVCE_RB_RPTR3 0x80d7
vce_4_0_offset.h 104 #define mmVCE_RB_RPTR3 0x0ad7
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v3_0.c 99 v = RREG32(mmVCE_RB_RPTR3);
300 WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
amdgpu_vce_v4_0.c 77 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
365 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));

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