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    Searched refs:mmVCE_STATUS (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h 51 #define mmVCE_STATUS 0x8001
vce_2_0_d.h 29 #define mmVCE_STATUS 0x8001
vce_3_0_d.h 29 #define mmVCE_STATUS 0x8001
vce_4_0_offset.h 30 #define mmVCE_STATUS 0x0a01
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v2_0.c 127 uint32_t status = RREG32(mmVCE_STATUS);
241 WREG32_P(mmVCE_STATUS, 1, ~1);
270 WREG32_P(mmVCE_STATUS, 0, ~1);
310 WREG32(mmVCE_STATUS, 0);
amdgpu_vce_v4_0.c 138 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));
311 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
318 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
323 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
372 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,
384 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
406 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0);
723 if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
728 if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
amdgpu_vce_v3_0.c 246 uint32_t status = RREG32(mmVCE_STATUS);
356 WREG32(mmVCE_STATUS, 0);
629 if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
634 if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

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