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Searched refs:mmVCE_UENC_CLOCK_GATING (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h	`55 #define mmVCE_UENC_CLOCK_GATING 0x816F`
vce_2_0_d.h	`53 #define mmVCE_UENC_CLOCK_GATING 0x81ef`
vce_3_0_d.h	`57 #define mmVCE_UENC_CLOCK_GATING 0x81ef`
vce_4_0_offset.h	`118 #define mmVCE_UENC_CLOCK_GATING 0x0bef`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v2_0.c	`162 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); 165 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); 178 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); 324 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); 326 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); 339 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); 342 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); 370 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING); 374 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);`
amdgpu_vce_v3_0.c	`192 data = RREG32(mmVCE_UENC_CLOCK_GATING); 195 WREG32(mmVCE_UENC_CLOCK_GATING, data); 218 data = RREG32(mmVCE_UENC_CLOCK_GATING); 220 WREG32(mmVCE_UENC_CLOCK_GATING, data); 534 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); 769 data = RREG32(mmVCE_UENC_CLOCK_GATING); 772 WREG32(mmVCE_UENC_CLOCK_GATING, data);`
amdgpu_vce_v4_0.c	615 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000); 833 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); 836 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); 859 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); 861 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); 924 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING); 927 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data);

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