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    Searched refs:mmVCE_UENC_REG_CLOCK_GATING (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h 57 #define mmVCE_UENC_REG_CLOCK_GATING 0x8170
vce_2_0_d.h 54 #define mmVCE_UENC_REG_CLOCK_GATING 0x81f0
vce_3_0_d.h 58 #define mmVCE_UENC_REG_CLOCK_GATING 0x81f0
vce_4_0_offset.h 120 #define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v2_0.c 179 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
328 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
330 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
344 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
346 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
376 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
379 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
382 WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
amdgpu_vce_v3_0.c 202 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
204 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
226 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
228 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
535 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
amdgpu_vce_v4_0.c 616 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);
843 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
845 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);
867 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
869 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);

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