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Searched refs:mmVCE_VCPU_CACHE_OFFSET1 (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h	`59 #define mmVCE_VCPU_CACHE_OFFSET1 0x800B`
vce_2_0_d.h	`33 #define mmVCE_VCPU_CACHE_OFFSET1 0x800b`
vce_3_0_d.h	`33 #define mmVCE_VCPU_CACHE_OFFSET1 0x800b`
vce_4_0_offset.h	`38 #define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v2_0.c	`197 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);`
amdgpu_vce_v3_0.c	`559 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); 568 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);`
amdgpu_vce_v4_0.c	`295 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), 650 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) \| (1 << 24));`

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