HomeSort by: relevance | last modified time | path
    Searched refs:mmVCE_VCPU_CNTL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h 64 #define mmVCE_VCPU_CNTL 0x8005
vce_2_0_d.h 30 #define mmVCE_VCPU_CNTL 0x8005
vce_3_0_d.h 30 #define mmVCE_VCPU_CNTL 0x8005
vce_4_0_offset.h 32 #define mmVCE_VCPU_CNTL 0x0a05
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v3_0.c 311 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
348 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
543 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
amdgpu_vce_v4_0.c 313 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),
375 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);
398 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);
amdgpu_vce_v2_0.c 305 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);

Completed in 14 milliseconds