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    Searched refs:mmVLINE_STATUS (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v6_0.c 2976 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 4455 #define mmVLINE_STATUS 0x1AEE

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